Medical Electronics Manufacturing Fall 1999

SIGNAL CORRECTION

Delay lines can play a crucial role in designing medical electronics that incorporate timing devices such as digital signal processors.

Dennis Fitzsimmons

Delay lines—compact discrete components that pack a cabinetful of utility into a package the size of a cufflink—are enjoying a renaissance thanks to the increased use of digital signal processing and other embedded systems in modern medical electronics.

A logic delay module. Taps allow for adjustment of the delay time in 5-ns intervals. The total possible delay is 40 ns.

Delay lines have always delivered cost-effective timing solutions, including adjusting and normalizing circuit timing, providing fixed or programmable pulses from various pulse-width inputs, supplying instant start-up clocks or multiple clock cycles during a single master clock cycle, and filtering out digital spikes. Delay lines are commonly found in many scanning and imaging systems where they have helped in signal correction. A delay line slows the signal just enough to allow the timing of the pulse edges to be in perfect sync.

The subtleties of designing and specifying delay lines into specific circuit applications can be confusing. This article provides some guidelines to help medical equipment engineers incorporate delay lines into circuits to obtain the maximum performance from these components and avoid application errors that can lead to missed delivery dates.

Passive and Active Delay Lines

Passive delay lines are less well known and less understood than their active counterparts. Passive delay lines, which are made up of capacitors and inductors, are intended for use in analog applications. With passive components, design engineers must be concerned with driving the line, providing the correct termination (or pick-off) of the signal, and compensating for line attenuation.

Active delay lines, however, are digital, and thus incorporate integrated circuits into their package. The inputs and outputs, therefore, are already interfaced and characterized for a particular logic family: transistor transistor logic (TTL), emitter-coupled logic, (ECL), or complementary metal-oxide semiconductor (CMOS).

Engineers must consider inherent frequency constraints, particularly with passive designs. A passive delay line is designed for a specific frequency range, ranging from dc to an upper 3-dB cutoff frequency. In order to realize the line's maximum capabilities, input pulse rise time must always be faster than the specified output rise time of any line. For best results, the operating frequency should be lower than the 3-dB frequency of the line. Using the line near the 3-dB point results in more overshoot, attenuation, and distortion caused by ringing.

When using passive delay lines, designers must also factor in stray capacitance. The circuit must be evaluated to determine whether impedance mismatching or stray inductive or capacitive buildup has occurred in the circuit board because of the combination of discreet components. Low-impedance delay lines are characterized by relatively high capacitive elements in relation to low inductive elements. High-impedance delay lines have relatively low capacitive elements and high inductive elements.

For example, consider a short-time-delay, high-impedance delay line with 10 taps whose external circuitry adds 2 pF per tap for a total of 20 pF of capacitance. The additional capacitance will affect delay-time accuracy and impedance on the delay line, and, in some cases, can affect delay accuracy or change impedance by as much as 20%.

Specifications

It is important to remember that a delay line acts as a multipole low-pass filter. This becomes a problem when designers attempt to delay signals with higher frequency characteristics than the delay line is capable of passing. A change in the input waveform caused by variance in the group delay can significantly affect accuracy, especially at higher frequencies. Specifications should always include the applied frequency and intended use to ensure that suppliers provide the appropriate delay lines.

The overall delay time is the duration between the reference (or threshold) level of the leading edge of the input pulse and the reference or threshold level of the leading edge of the output pulse. Analog delay lines are measured at the 50% point of the signal, whereas digital delay lines use a fixed voltage level, typically the logic threshold voltage.

Crucial mistakes can be avoided simply by exercising caution when specifying a delay line. Failing to specify the falling-edge accuracy is probably the most common omission. Many designs require a specific pulse width from input to output. To maintain the duration of the input pulse width, both the rising- and falling-edge timing accuracy must be specified. Standard off-the-shelf delay lines are typically calibrated only for rising-edge accuracy.

Figure 1. Waveform of rising and falling edges of the pulse and leading and trailing edges of the positive and negative pulses.

Identifying leading and trailing edges requires determining whether the reference pulse is positive or negative. Similarly, specifying input frequency is often affected by duty cycle, pulse width, and pulse spacing. Pulse width is the duration of the pulse itself; pulse spacing is the time between pulses. It is important to ascertain whether the pulse is negative or positive to ensure proper performance. A matching polarity must be specified to ensure that the delay line will perform according to optimum specifications. Rise time (or fall time) is the time required for the voltage to change from one level to another. In analog lines, the voltage levels are 10% and 90%; most TTL systems, for example, specify levels at 0.8 and 2.0 volts. Other logic circuits may differ (Figure 1).

Relying on Taps

Taps provide multiple pick-off points to allow for incremental timing adjustments over the delay line. Engineers can ensure design success by relying on the flexibility afforded by a delay line with several taps. In a passive (analog) delay line, these taps are simply connections between the inductor-capacitor arrays that are connected to external pins in the package. As many as 20 equally spaced taps can be included in a single passive package.

Hundreds of standard models of active and passive tapped delay lines are available with delays from 1 to 1000 nanoseconds and with 1, 3, 5, or 10 incremental taps. Such versatility can be useful in circuits where a timing range is established, but variances in other components need to be compensated for. Jumping to a different tap adjusts the circuit timing without having to replace the delay line.

Fine Tuning and Frequency Control

Other tools, such as programmable delay lines, can be incorporated when a delay needs to be dialed in after assembly, or even when timing needs to be adjusted dynamically. To determine the minimum and maximum timing limits, for example, a piece of automated test equipment could vary the timing parameters of the device under test.

For other frequency-control products, such as crystal-controlled oscillators, using delay lines can increase options for meeting certain design challenges. For example, delay-line waveform generators can start and stop instantly, allowing them to synchronize to external events. Pixel clock delay lines can resynchronize at the beginning of each sweep line across a video screen. Digital square wave generators can replace crystals in applications that do not require a crystal's tight frequency control. Delay-line waveform generators typically demonstrate from 0.5 to 2% frequency tolerances.

Rick Pray, engineer at Robison Electronics/EC₂, traces a component.

Digital frequency multiplier modules (DFMMs) are used in applications where an exact frequency multiple is desired from a given base frequency. The correction system used in a DFMM delay line can be used in many cases where a phase-locked loop (PLL) would be incorporated. Typical uses include clock frequency multiplication when other processes need to be clocked during the main cycle and code or burst synchronizing in which a continuous output clock is required but input clocks may be missing one or more edges. The synchronizer in the delay line compensates for all phase errors at one time, whereas a PLL error signal gradually shifts the output frequency. As long as the DFMM increases the base frequency no more than 10 times, the output waveform jitter is minimal.

Conclusion

Engineers should discuss delay-line specifications with the supplier early in the design stage. A conscientious supplier can often suggest a product that will simplify the circuit design or optimize performance. Careful attention to these guidelines can result in optimal performance from delay lines in medical electronics, especially when digital signal processing is involved. The overall result should be a finished product that is delivered on time, meets the customer's requirements, and performs as expected in the field.

Dennis Fitzsimmons is engineering manager for Engineered Components Co. (San Luis Obispo, CA).

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