Medical Electronics Manufacturing Spring 1999
Chip-scale packaging is emerging as a desirable option for performance-driven small-form-factor medical devices.
Among the many advanced electronics packaging forms introduced during the past few years, chip-scale packaging (CSP) has evolved as an increasingly suitable option for use in performance-driven printed circuit board assembly (PCBA) products. The past 18 months could even be called the CSP revolution, reflecting tremendous activity among package developers, potential users, and assembly providers.
Chip-scale packaging provides PCBA designers and manufacturers with the mainstream assembly infrastructure compatibility and the performance advantages of surface-mount technology (SMT). Consequently, the medical device industry has now begun to embrace CSP as a desirable electronics package for use in its performance-driven small-form-factor (SFF) PCBA products. However, CSP assembly integration into medical electronics products presents a greater challenge for achieving reliability compliance than it has for commodity products such as personal computers.
CSP Performance Advantages
In contrast to leaded SMT packaging, CSP provides designers with enhanced performance for electrical, thermal, and mechanical characteristics. CSP uses the same type of interconnect attachment method to the PCBA as the popular—yet physically larger—ball grid array (BGA) packaging. Since 1993, the electronics packaging and assembly industry has seen BGA packaging evolve into a dependable option that offers increased input/output (I/O) density and enables a level of assembly robustness far beyond that of the peripheral leaded quad flat packs (QFPs) available at that time.
CSP presents many of the same advantages as BGA packaging, which has a common solder ball grid pitching of 1.27 mm, yet offers a significantly smaller physical size. The most common CSP solder ball grid pitch is 0.78 mm. CSP devices are available with pitching down to 0.4 mm, which provides even more I/O density. This smaller physical size presents appealing prospects for the evolution of SFF medical products, especially in the growing consumer handheld and in-home market segments. In addition, CSP offers increased electrical performance because of available alternatives to conventional wire-bonded die-attachment methods common for BGA packaging. These alternative die-attachment options include thermocompression bonding, solder castillation reflow, and solder-bumped flip-chip methods (see Figure 1).
Figure 1. Quad flat pack, ball grid array, chip-scale packaging, and flip-chip package samples.
In the flip-chip method, the die is flipped upside down for attachment. Considered the ultimate performance package, flip-chip packaging offers a more conservative dimension than BGA packaging for bump pitch. The flip-chip method offers direct-bump interconnects, allowing for the shortest possible conductor lengths (to accommodate the lack of a wire for die-to-carrier substrate interface). The lack of extra conductor length mitigates circuit parasitics and noise problems within a circuit application. The flipped orientation makes the entire upper surface of the die accessible for direct thermal transfer, allowing optimum thermal relief. Thermal transfer can be achieved through convection, conduction, or some combination.
Another advantage of flip-chip packaging is its mechanical size. It represents only the footprint of the silicon die itself, with minimal height because of its bump interconnect method. Hence, flip-chip packaging offers the best electrical, thermal, and mechanical advantages. Unfortunately, the required infrastructure that enables flip-chip die bumping and subsequent assembly is far from being considered mature for cost-effective product implementation. Therefore, manufacturers are opting for CSP based on the perception that it can provide many flip-chip performance advantages in the near term, as well as fit within an SMT infrastructure.
CSP Selection and Assembly Integration
It may appear that CSP design integration is an obvious solution for use in SFF products. However, implementing successful assembly integration and process controls is by no means simple. The first consideration should be the diversity of CSP styles. Many options are available in varying degrees of complexity. Currently, 22 patented or patent-pending CSP variations are available. Table I summarizes various characteristics and options. Having such a variety available has contributed to the reasons CSP has not achieved the mainstream deployment enjoyed by kindred BGA devices. The options often confuse even the most knowledgeable product designers and systems developers.
|Interposer/Substrate||Secondary Interconnect||Die-Attachment Method|
|Flex laminate||Castillation||Wire bond|
|Rigid laminate||Solder ball||Thermocompression|
(solid or coated)
|None (die only)|
Table I. Chip-scale package styles.
Selecting a CSP style should be based on required performance as well as on known or anticipated systems reliability concerns. Designers and developers should assess the product's I/O needs and compare them to the available CSP options. Selection should account for an already-tooled standard I/O pattern and outline size. Reliability testing should be completed or in progress and trending favorably. To incorporate concurrent engineering, it is best to involve eventual manufacturing services at the time of packaging selection and qualification. The manufacturer may be able to provide input regarding processibility and postassembly reliability. Many such services independently assess CSP options. These assessments often reflect the assembly and follow-up reliability testing using a custom-developed process test vehicle (see Figure 2). The firsthand knowledge gained through such experimentation can save significant time and development costs.
Figure 2. Chip-scale packaging test vehicle.
Successful assembly integration and process control begin at the printed wiring board (PWB) design stage. The PWB design layout must account for a CSP land pattern that provides an efficient electrical trace route. The layout must also play a primary role in determining hole location and sizing, solder-paste damming, thermal (copper) balance, and external solderable surface finishes. These PWB design parameters greatly affect the construction technique, substrate costs, and subsequent assembly success and reliability at the PCBA level.
CSP integration is not always synonymous with achieving lower costs. Reducing costs using CSP largely depends on the package style, I/O density, PCBA complexity, and product volume. Successful CSP assembly can entail an intricate process at each of the three SMT assembly steps: stencil design, placement, and solder reflow.
Stencil design greatly influences the overall success of integration at all three assembly steps. Stencil complexity is reflected in the I/O count, grid pitch, and solder ball size of the CSP itself. Stencil aperture shape, sizing, and machining processes all contribute significantly to process outcome. Developers should facilitate an experimental design phase during PCBA builds that addresses multiple stencil design and fabrication options. Stencil design guidelines and fabrication effects are not predetermined for CSP as they are for other SMT package options.
Placement processes for CSP focus on accurate pick, vision evaluation (for x, y, and ), and z stroke for controllable tack. Although vision files can be assembled for specific package styles, nozzle selection may sometimes present a challenge, depending on the surface area available for vacuum access and the topography of that area. It is expected that all CSP devices with I/O counts higher than 100 will continue to use industry-standard matrix trays; the use of pocketed tape appears desirable only for high-volume commodity applications. Tacking a device onto a solder-pasted land pattern is a sensitive step. Because partial or full array grid pitches at 0.6 mm may evolve into a standard for application-specific integrated circuits (ASICs), a process challenge exists that was not recognized in earlier, simpler SMT packages. This process entails placing parts on and through the board. Fortunately, most current placement equipment is outfitted or can be retrofitted to accommodate CSP handling and controlled tack (see Figure 3).
Figure 3. Chip-scale packaging device being picked by a placement machine.
Finally, solder reflow becomes more involved because of the smaller interconnect size, reduced mass, and low-profile clearance of CSPs. Controlling convection force is key to successful solder reflow in current forced-air convection reflow ovens. If convection force is left uncontrolled, excess air-flow can actually eject devices from the PCBA.
Selecting solder paste flux chemistry and identifying subsequent reliability effects can significantly affect assembly. For higher-density packaging, a recent trend has been toward greater use of aqueous fluxes (water washable with no saponifiers). No-clean solder fluxes often tend to ball more than aqueous chemistries do. Therefore, as the density of BGA packaging and CSP hidden connections have increased, so has the use of aqueous fluxes. Although general reliability tests point to low ionic contamination and high surface insulation resistance (SIR) values on aqueous fluxes, many device manufacturers use no-clean flux chemistries to avoid possible excess solids that promote dendritic growth. Much SIR research analyzing the risks associated with dendritic growth has been conducted. Several years ago, the nonlinear relationship of ionic contamination, SIR values, and circuit geometries was determined. However, because of the increased interest in CSP and the associated severely reduced circuit sizes, it is likely that many product developers and assembly providers will be conducting additional experiments to validate the relationships among these three parameters.
The following guidelines are designed to address perceived adverse effects related to the integration of CSP into PCBA medical products. To comply with FDA regulations, special procedures should be implemented to monitor in-process and final quality trends. In addition, programs should be in place for ongoing evaluation of both material and product reliability. Both manufacturing and quality control personnel should participate in the early development of special controls, test methods, inspection methods, and training programs.
Although CSP is capturing much attention for use in performance-driven SFF medical product applications, its implementation presents challenges. In addition, FDA's design control regulations increase the complexity and risk of designing devices using this technology. To achieve the most success with CSP in medical products, manufacturers should institute concurrent engineering, which enables the collaboration of design and development personnel with manufacturing services. Early concurrent engineering can minimize scheduling conflicts, manufacturing costs, and reliability concerns, and help ensure product development success.
LeRoy Jarvis was formerly vice president of manufacturing and technology for K*TEC Electronics (Sugar Land, TX).
In the MEM Spring Issue, an article entitled "The Manufacturing Impact of Chip-Scale Packaging in PCBA Medical Products" was published with the author incorrectly shown as Cameron Presley. The article was authored by Leroy Jarvis, vice president of manufacturing and technology at K*Tec Electronics, Sugar Land, TX, at the time the article was written for K*Tec Electronics. We regret this error and any confusion which may have occurred.