The global electronics industry is exhibiting a widespread interest in embedded passives. This interest can be attributed to three primary benefits of the technology. First, embedded passives have far less parasitic inductance than do discrete components, which enables electrical performance advantages in high-speed digital applications. Second, embedding saves surface real estate, which allows for board size reductions. Third, the incremental cost of embedding additional passive components is typically negligible, which suggests the potential for system cost reduction in designs with high passive component counts.

Designers of high-speed digital devices, including those in medical electronics, often choose a copper-clad embedded capacitance material that uses an ultrathin dialectric material with a high dielectric constant between the copper planes. The material can deliver a capacitance density of up to 10 nF/in2. This material can help manufacturers achieve high performance and rugged reliability demanded by end-users.

Manufacturers should strive to understand this ultrathin, laminate embedded capacitance material and how it can improve electrical performance, reduce board size by replacing discrete capacitors, and increase printed circuit board (PCB) reliability.

 

Electrical Performance Advantages

The semiconductor industry is characterized by shrinking feature sizes and rising transistor counts. Along with these changes come lower operating voltages and increased current requirements. These trends place severe demands on the ability of the circuit board to distribute power to the surface-mounted active devices. The circuit board’s power distribution system must meet increasingly low impedance requirements.

The typical components of a circuit board’s power distribution system include a switching power supply, bulk decoupling capacitors, high-frequency decoupling capacitors, and inner layer power and ground planes. One of the best ways to improve power distribution (i.e., decrease impedance) is to use closely spaced power and ground planes within the multilayer board stack-up. This approach has been used for 25 years with FR-4 dielectrics in the range of 2–4 mil in thickness.

Using thinner dielectrics with high dielectric constants can significantly increase the effectiveness of the approach. Standard FR-4 technology is limited to 2-mil thickness, a dielectric constant value (k) of approximately 4, and a capacitance density of only 0.5 nF/in2. Thinner (<25 µm) dielectric materials, especially those filled with high-dielectric ceramic particles, are being used to address power distribution in high-frequency designs.

In combination, these features deliver a high capacitance density of 6.4–10 nF/in2 and, when used for decoupling high-speed digital electronics, offer the following:

• Lowering impedance of power distribution system.

• Dampening board resonances.

• Reducing noise on power planes.

• Reducing radiated emissions.

• Replacing large numbers of discrete decoupling capacitors.

• Eliminating large numbers of solder joints and their associated vias and traces.

From a designer’s perspective, noise margins are increased, which can translate into improved performance and less engineering time devoted to troubleshooting and fixing noise problems. In addition, the component count reduction saves time in board layout.

This article presents several examples of high-speed digital board designs that used ultrathin dielectric with a k of 16 for distributed decoupling (power-ground) in multilayer rigid PCBs.

In Figure 1, the self-impedance of a 5 × 10-in. multilayer bare board with an ultrathin (8 µm) dielectric between the power and ground planes is compared with the same board design with 50-µm (2-mil)-thick FR-4 and 25-µm (1-mil)-thick FR-4 dielectric between the power and ground planes. At lower frequencies, the self-impedance of the ultrathin laminate material is more than an order of magnitude lower than that of 1- or 2-mil-thick FR-4. This is due to the higher capacitance density of the ultrathin material (~10 nF/in2 versus ~0.5–1 nF/in2). At higher frequencies, the self-impedance of the ultrathin dielectric material is also significantly lower than that of the 1- or 2-mil FR-4 laminate. This is primarily due to the significantly lower self-inductance of the ultrathin material. Finally, in the 100 MHz–1 GHz frequency range, both the 1-mil and 2-mil FR-4 laminates show large impedance spikes caused by board resonances. These are undesirable because the noise associated with these impedance spikes can trigger false switching, compromise signal integrity, and cause electromagnetic interference (EMI). With the ultrathin dielectric, the board resonances are almost completely dampened due to the high copper losses of closely spaced power and ground planes at high frequencies.

In Figure 2, the self-impedance of ultrathin embedded capacitor laminates with dielectric thickness of 8 μm, 12 µm, and 24 µm, all with a k of 16, are compared with a 50-µm FR-4 laminate with a k of ~4 on this same board design. Here it can be seen that the 24-µm material with a k of 16 performs much better than a 25-µm laminate with a k of 4 (shown in Figure 1). Additionally, the 12-µm material performed nearly as well as the 8-µm material in providing a low impedance in the preresonance frequency as well as dampening the noise due to board resonances at higher frequencies.

In Figure 3, the close-field radiation was measured on the same 5 × 10-in. board. The measurement was taken on the long (10 in.) side of the board, approximately one-half inch from its edge. Figure 3 shows that the ultrathin dielectric is responsible for lowering the EMI (noise seen on all samples at >200 MHz is due to cable effects and should be ignored).

In another example, the S21, or transfer function of noise from one part of a board to another, was measured (a lower S21 is better). The board size was 10 × 12 in. A typical four-metal-layer board with 35-mil separation between power (layer 2) and ground (layer 3) was compared with a board with a 16-µm-thick (k of 16) dielectric layer between power and ground. The typical board had 99 0.1-µF surface-mount decoupling capacitors assembled uniformly over the board. The ultrathin embedded capacitance board had no decoupling capacitors mounted.

Even with a large amount of discrete decoupling capacitance (9900 nF), the typical board was only able to achieve low S21 at below several hundred megahertz. The board with ultrathin embedded capacitance had an extremely low S21 over the entire frequency range (up to 15 GHz). In the frequency range over 500 MHz, the ultrathin embedded capacitance board had a S21 of about 40 dB less than that of the typical board.

In yet another example, noise versus frequency was measured on a fully assembled daughter board with an approximate size of 5 × 5 in. The noise was measured on the 1.5-V plane up to a frequency of ~1.5 GHz. The daughter card had a MIPS R14K processor running at 550 MHz and nine secondary cache SRAMs running at 275 MHz.

Two board designs were compared. The first had a 3-mil FR-4 dielectric thickness between power and ground planes and the second board had an 8-µm dielectric thickness (k of 16) between power and ground planes. The board with the ultrathin dielectric demonstrated significantly less noise at all frequencies above ~50 MHz. At frequencies above 500 MHz, the board with the 3-mil FR-4 still had a large amount of noise whereas the board with the ultrathin dielectric had extremely effective noise dampening above 500 MHz. Over the frequency range measured, the board with the 8-µm dielectric (k of 16) had 13.3 dB less noise than that of the board with the 3-mil FR-4 power-ground plane.

The peak-to-peak voltage ripple was also measured on these boards. For the case of the board with the 3-mil FR-4 power-ground plane spacing, the peak-to-peak noise was 235 mV (15.7% of 1.5 V). For the board with the 8-µm power-ground spacing, the voltage ripple was 114 mV (7.6% of 1.5 V), or slightly less than one-half of that of the 3-mil FR-4 board.

Lastly, as part of the National Center for Manufacturing and Sciences Embedded Decoupling Capacitance industry consortia, power bus noise and voltage fluctuation were measured by the Missouri University of Science and Technology. The six-metal-layer boards were 2 × 3 in. in size. Each contained a 50-MHz oscillator, a 22-µF bulk decoupling capacitor, eight octal clock drivers, and a number of load capacitors.

The materials used for layers 3 (power) and 4 (ground) of the boards were various embedded capacitance laminate materials including 2-mil FR-4 (BC2000TM) and a leading brand of embedded capacitor material (5 µm; k of 16). These boards were compared with a baseline board with an approximate 4-mil FR-4 laminate used for the power-ground core.

None of the boards with embedded capacitance laminates were surface mounted with any decoupling capacitors beyond the 22-µF bulk decoupling capacitor. The baseline board was surface mounted with 33, 0.01-µF high-frequency decoupling capacitors (total of 330 nF). The amount of embedded capacitance for the 2-mil embedded capacitance board was ~3 nF and was ~107 nF for the 5-µm embedded capacitance laminate board.

First, the 5-µm laminate board (with no decoupling capacitors) was compared with the 4-mil FR-4 baseline board, with and without the 33 0.01 µF decoupling capacitors over the frequency range of 1 MHz–5 GHz. Figure 4 shows that the 0.01-µF decoupling caps did a reasonably good job decoupling in the 1 MHz–1 GHz range on average. However, at frequencies beyond 1 GHz, the decoupling capacitors are ineffective due to their high inductance. The 5-µm laminate did a much better job of decoupling across the entire frequency range (10–40 dB noise reduction) even though it had only one-third of the capacitance (107 nF versus 330 nF) of the surface-mounted decoupling capacitors.

Power bus voltage ripple measurements were also taken on the embedded capacitor and baseline six metal layer boards. Figure 4 shows the amount of voltage fluctuation from the nominal 3.3-V power plane in the time domain for the 4-mil FR-4 baseline board with 33 decoupling capacitors, the 2-mil FR-4 board and the 5-µm board.

The peak-to-peak voltage ripple for these boards is shown in Table I. The board with the 5-µm embedded capacitance material had less than one-half the voltage ripple even though it had less than one-third of the capacitance of the surface-mounted caps. The board with the 2-mil FR-4 embedded capacitance had such a large voltage fluctuation that it did not function properly. This was due to the lack of sufficient embedded capacitance to provide charge to the IC until the bulk decoupling capacitor could provide charge.

 

Board Size Reduction

Ultrathin embedded capacitor laminate material has been successfully implemented on several OEM designs to replace large quantities of discrete decoupling capacitors from the board surface. Some of the data from a survey of these board designs are shown in Table II (p. 26). In every case, the use of the distributed embedded capacitance allowed the elimination of at least 60% of the discrete capacitors. In most cases it was 75%, and in two cases, all of the discrete decoupling capacitors were removed. In one case, more than 500 capacitors were eliminated from the board. Plus, only a very small amount of embedded capacitance was needed to replace a large amount of discrete capacitance (each nF of embedded capacitance replaced 10–40 nF of discrete capacitance).

These data suggest that by using a few hundred nanofarads of low-inductance, ultrathin embedded distributed capacitance (as a power-ground core or cores), a large number of decoupling capacitors can be removed. It is strongly believed that all decoupling capacitors <0.1 µF can be removed as well as the majority of 0.1-µF decoupling capacitors. For high-speed designs, this can result in the removal of hundreds of capacitors. This is significant for portable and medical products for which board area reduction is paramount.

Reliability

Much reliability testing of ultrathin embedded capacitors has been completed over the last 15 years. This includes numerous designs from a large number of PCB fabricators. The ultrathin (k of 16) embedded capacitor material has shown to be a reliable material for use in multilayer rigid PCBs. These designs have consisted of anywhere from four to more than 40 metal layers with one to approximately 12 embedded capacitor cores. Since 1996, many hundreds of multilayer boards from more than a dozen PCB fabricators have been tested using industry reliability tests.

 

Cost Reduction

The use of ultrathin power-ground cores for embedded distributed capacitance can potentially lower the system cost of products. However, assessment of such cost reductions is complex. Ultrathin embedded capacitor materials cost significantly more than standard laminate material. They can also cost significantly more to process due to their material handling requirements. These costs may be offset by the ability to get more boards on a panel or by a reduction in the total number of board layers. It may also be possible to combine two or more boards in a system onto the same board. However, in general, unless there is significant board size reduction, the costs of embedded capacitor boards are significantly more than traditional bare boards.

As previously mentioned, ultrathin power-ground cores can also be used to eliminate discrete power supply decoupling capacitors from the board surface. When all of the costs associated with the drilling of the capacitor vias and the purchase and assembly of the discrete capacitors (assembly, inspection, rework, etc.) are combined, the result can be a significant cost reduction per board, especially if assembly is reduced from double to single sided.

There may be additional cost reductions available with ultrathin embedded capacitor materials. Embedded capacitor materials can reduce or eliminate electromagnetic compatibility issues. This may save on costs associated with EMI shielding and containment. The materials may also enable fewer or shorter design cycles than a typical process, further reducing cost. Such benefits are difficult to quantify.

Removing the discrete capacitors improves board long-term reliability because solder joint and via failures are reduced. Bare board yields can improve due to the elimination of vias, board size reduction, and increased routing space. In contrast, material handling or other processing issues with embedded capacitor materials could have a significant negative effect on board yield if care is not taken in board design and processing. Another factor is that rework is not possible with embedded capacitor materials once the material has been laminated into a board.

In summary, some inputs into the cost comparison can be easily quantified but others cannot. Some factors increase the system-level cost while others decrease it. There are also a number of inputs that can affect system cost depending on the material involved and the design and manufacture of the boards.

When considering potential cost reduction with embedded capacitor materials, keep the following in mind:

• Consider total system cost, not bare board or assembled board costs.

• Compare not only what the system level cost is at the current time but also what it will be throughout the life of the product.

• As the supply chain grows, gains experience, and becomes more competitive, the costs associated with the use of these materials will continue to decrease, allowing for system cost reductions in a variety of applications.

 

Conclusion

Embedded passives are of significant interest today for electronic medical device OEMs that are looking to improve the electrical performance and reliability, reduce EMI, reduce the size, or lower the overall system cost of their products. Ultrathin embedded capacitor materials with increased dielectric constants can help OEMs achieve those objectives.

 

Joel S. Peiffer is an advanced engineering specialist with 3M’s Electronics Solutions Division (Austin, TX). He can be reached at jspeiffer@mmm.com.