Originally Published MEM Spring 2005
A variety of packaging options and processes enable medical device manufacturers to make the right choice to achieve the desired functionality and performance.
|Products courtesy of TESSERA INC. Photo by RONI RAMOS|
A primary challenge that electronics manufacturers—including those in the medical device industry—face is developing products that meet all performance and functionality expectations, within budget and without increasing product size. Handheld communication and entertainment products continue to dominate the consumer markets worldwide, with companies offering more and more features or capabilities each generation.
And even though the actual functionality of the new product offering expands, customers expect each new generation to be smaller and lighter than its predecessor. Expanded function-ality, however, requires more-complex electronics and greater memory capacity. Increasing functional capability, on the other hand, can adversely affect a product's size as well as manufacturing cost. This article examines die-stack-packaging options, including 3-D packaging, folded multiple-die packaging, and stacked packaging. It looks at the available stacking processes to help medical electronics manufacturers select the right process for a given application.
The increase in electronic functionality can be achieved through the development of more-complex silicon integration, but that route generally requires a great deal of capital resources and time. For that reason, many manufacturers rely heavily on more-innovative package solutions, including solutions for integrating a number of already-proven functional elements within a single-package outline. To achieve system-level integration and miniaturization goals, companies can now rely on a combination of miniature single-die chip-size and chip-scale integrated circuit (IC) packaging, as well as multiple-die package solutions.
The impetus for developing higher-density IC packaging for medical electronics is to furnish greater functionality, be smaller than its predecessors, and provide a higher level of performance and reliability. To address functionality and size, a number of companies are already combining single-die packaging and various forms of multiple-die packaging. An example is the growing availability of high-density memory in which the IC devices are functionally the same, offering dynamic random-access memory (DRAM), flash memory, or basic combinations of the two. The most common method for producing these multiple-die components is die stacking, or package stacking.
|Products courtesy of TESSERA INC. Photo by RONI RAMOS
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The die-stack process allows the supplier to rapidly develop basic multiple-die combinations. These are most practical for a mature, higher-yielding die. The benefit to the medical device manufacturer is increased functionality in a smaller space; often two or three die are encased in a single fine-pitch ball-grid array (FBGA) package outline. The most efficient die-stack package assembly process uses die combinations in which die of various sizes can be mounted sequentially in a pyramid fashion.
When the same size die are stacked, the die must be individually mounted and wire-bonded before adding the next die in the stack. However, to clear the wire-bond loop on the lower die, a spacer must be provided between active die layers.
In addition, unless all of the unpackaged bare die have a relatively high yield or are pretested and known to be good before assembly, multiple-die package yields may be well below the acceptable levels traditionally established for single-die packages. Multiple-die packages often have significant yield issues that are compounded with each IC die that is added to the stack or set. This effect is greater when combining high-yield devices with lower-yield devices. This factor further supports the importance of using die that are pretested or known to be good.
Memory die, such as flash and static random-access memory (SRAM), have relatively high fabrication yields. Some companies waive die-level testing altogether, but damage to the die can occur during any phase of package assembly processing and handling.
Two- or three-die assembly may provide a reasonable assembly process yield, but as the die count increases, the failure probability increases as well. System-in-package (SiP) assemblies with 10 die that have yielded 95% good at first electrical test, for example, yield only 60% good after package-level assembly. In addition, assuming the failures in time to be 3%, approximately 20% of the assemblies that pass first electrical testing will fail in service.
3-D Package Methodology
|Figure 1. The µBGA package relies on an S profile that, when encapsulated, absorbs physical stress and strain that can occur between dissimilar materials when exposed to high and low operating temperatures.
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The technology developed for 3-D packaging is especially well suited for packaging ICs that need a very low finished profile height. The chip-size µBGA package, for example, adapts a unique lead-bond process. The methodology is recognized as one of the most reliable package interconnect techniques, offering a very close low-profile coupling between the die and the substrate, which minimizes both signal inductance and resistance. The lead design employs a narrow section of the copper foil bridging across an ablated section of the flexible polyimide film substrate. The exposed conductor is plated with a thin layer of gold alloy to accommodate the die-to-substrate interface. During the lead-bond process, the narrow cross section of the conductor breaks away from one edge of the ablated section of the substrate and is reshaped into an S-shaped profile (see Figure 1). It is then thermosonically connected to the corresponding die-bond pad. Although the lead-bond methodology was originally developed for single-die µBGA packaging, a number of multiple-die package applications that needed a low profile have been de- veloped using this technology as a foundation.
Folded Multiple-Die Packaging
Two, three, or more die can be combined into a single-package outline. This chip-scale package technology is an ideal solution for implanted electronics where substrate surface area is limited. For existing products, the folded package allows the expansion of memory capacity in the same footprint as a single package. The assembly process for the package begins with die attached onto a common multiple-site flexible substrate. The leads are simultaneously shaped and are terminated to each die pad. Following inspection, the die units are each encapsulated with a high-grade dielectric compound.
|Figure 2. A three-die µZ folded package outline is only slightly larger than the largest die in the set.
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The folding and bonding process takes place while all die units are retained in a multiple-package strip format. Before folding, an adhesive film is applied to the top surfaces of one row of die. The extended area is then folded over. The steps are repeated for the remaining extensions, which are secured for curing to complete the bonding process. Following a cure cycle, the solder ball contacts are applied, the folded strip is cleaned, and unit parts are finally singulated into individual packages and made ready for testing. The example shown in Figure 2 is a typical application for a three-die memory package that, when folded, uses no more area than a single-die package.
In preparation for the package process, individual package sections are first arranged in a rectangular strip-array format. The die are attached face down onto a thin dry-film adhesive provided at each site on the surface of the substrate. After all die are attached, the carrier-mounted strip is flipped over to allow access for the wire-bond process. One of the more mature processes for interconnecting the semiconductor and package substrate is the wire-bond. The process is primarily applied when the die is mounted face up, away from the substrate's surface. However, wire-bond can also be applied to die mounted face down against the package substrate. To accommodate facedown wire-bond, a slot must be provided in the substrate to access the bond pads on the die.
|Figure 3. The through-slot wire bond enables a very short interface between the die-bond pads and the µZ ball-stack package substrate.
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The example of the through-slot wire-bond package unit shown in Figure 3 is for a high-performance DRAM die with center-located bond pads. Following die attach and wire-bond, the bond window is encapsulated with an epoxy or silicone compound and, after curing, made ready for attaching the ball contacts.
To mount the ball contacts, flux paste is first printed onto the individual contact sites using a stencil process. A template fixture has proved efficient for distributing the ball contacts onto the flux, and the carrier-mounted units are gradually heated, employing a conductive furnace to complete the attachment process. To remove the flux residues, the assemblies are cleaned in a dynamic aqueous bath.
Following inspection, the individual devices are finally separated using a precision saw or laser, and are transferred to partitioned tray carriers. At this point, the devices can be electrically tested, graded, and laser marked.
The final 3-D configuration is accomplished by vertically joining two or more pretested single-package units into a low-profile multitiered package assembly.
Electrical Testing and Stacking Process
Electrical test and burn-in of memory can be performed before or after singulation. Test and burn-in prior to singulation, however, has proved most efficient. The initial electrical test duration is relatively short, but the burn-in, typically 125(infinity)C, can last from 4 to 12 hours. Following electrical test, the devices are marked, serialized, and sorted.
In preparation for the stacking process, the base or bottom packages are first transferred from the carrier tray to an alignment fixture. The actual stacking process begins with the transfer of the second-level package to a dip-fluxing station to uniformly coat the bottom half of the solder-ball contact. With flux applied, the packages are sequentially placed atop the base packages.
The stacking process may include two to eight package layers before transferring to a convection oven for mass reflow to complete the interlayer joining of the package levels. Following a final continuity test, the packages undergo a final physical inspection before transfer to shipping trays.
Already being adopted by several memory providers, the ball-stack package method has proved ideal for a number of the newer generations of high-speed DRAM applications and can be considered for the higher-density packaging of flash memory needed for long-term event monitoring in wearable or implanted medical electronic devices.
Stacking packaged die has proved less risky because the packages are tested before conversion to the stacked format. Package stacking of memory products actually began with lead-frame plastic-packaged ICs more than a decade ago. Even then, the market needed increased memory density for modules used for computing. Although the lead-frame stacking process cost was significantly greater than the basic packaging cost of the single-die component, the single-module substrate furnished double the memory capacity of a single-package set. Doubling the memory density saved the expense of additional circuit board modules and the connectors needed for interface to the host system.
Fold-Over and Stacked Packaging
|Figure 4. This stacked package enables board-level sequential assembly of components supplied from multiple sources.
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The example shown in Figure 4 shows the top surface of a face-up, wire-bonded fold-over packaged die with a mounting site on its top sur-face for mounting a commercially packaged memory device. Specifically developed for SiP applications requiring more-complex mixed-technology functions, the package method enables the efficient integration of widely diverse silicon technologies.
Microprocessors and memory, of course, have very different wafer process flows, but when the die can be individually packaged and tested before joining, overall package yield can be maximized. Through a process of folding and package stacking, two or more pretested parts become a single, high-yielding multiple-function component.
By providing the memory interface on the topside surface of the logic package, commercially available array packaged products can be soldered directly to the base package. For electrical interconnect, the substrate relies on a pattern of narrow gold-plated copper-core conductors for the interface (through gold wire) between the aluminum bond site on the die, the interconnection between die and, ultimately, the contact (solder ball) array needed for the circuit board attachment.
The actual interface between die sets typically requires two circuit layers to provide for higher wiring density. The substrate developed for the die package uses a high-grade polyimide film as its base structure. The two-metal-layer substrate enables very narrow circuit-routing features and provides optimized in-package interconnect. Although initially developed for adding memory variations, the fold-over extension of the base package can be configured to accept any number of fine-pitch-array package types.
The fold-over and stacked package offers a number of advantages to the device manufacturer. The package can be furnished prejoined ready for board mounting or as separate pretested package sections that can be joined during board-level assembly. Whether to join one package to the other before or during the board-level assembly process is a decision that may be influenced by the requirement for in-process configuration flexibility. For example, the base fold-over package can be furnished by vendor A while the memory sections of the stack are supplied by vendor B, C, or D. After all, memory functions are available from a greater number of sources, and the testing for memory is somewhat specialized.
Furthermore, this type of package can alleviate concerns of ownership of total quality and reliability. The logic device supplier is responsible for the logic, the memory manufacturers are responsible for the respective memory, and the board assembler is responsible for only the surface-mount attachment of the two. If the two sections are joined at the board-level assembly, the base fold-over package can be placed onto the board and the memory package placed sequentially onto the mating contact matrix of the base for simultaneous reflow soldering. This alternative allows the user to specify multiple variations (different memory functions, data rates, and so on), and it accommodates secondary sources of supply.
When adapting multiple-die configurations, risk is minimized because each package becomes a fully tested subsystem that can be certified by the supplier before board- or module-level assembly. The multiple-die package is often proven superior even to the system-on-chip (SoC) alternative, because it can economically integrate several different but complementary functions.
There are still challenges that need to be addressed. Many of these involve logistical and business issues that some in the industry are already solving. Challenges include strategies for cost-reduction and reliability improvement. Other issues involve design and analysis capabilities, thermal management, design cost, system test, and known-good-die purchasing portfolio. For a number of high-volume applications, it may be practical to combine both SoC and SiP to achieve specific economical goals.
Another issue is the acknowledgement of and respect for each developing company's innovative intellectual property (IP) and the need for improved cooperation among the package manufacturers, semiconductor device suppliers, and the systems companies.
It is imperative that, as the SiP sector continues to grow, all of the parties involved find ways to work with each other to make sure that they minimize risk, while ensuring rapid deployment of needed multiple-function products into the marketplace.
Vern Solberg is senior application engineer for Tessera Inc. (San Jose). He can be reached at firstname.lastname@example.org
Copyright ©2005 Medical Electronics Manufacturing