- Data Acquisition/Memory [4]
- Design [5]
- Feature [6]
Originally Published MEM Spring 2003
ELECTRONIC PACKAGING
From system-in-a-package to multichip packaging, the medical electronics industry is poised to take advantage of the latest packaging and memory advancements originally developed for wireless communications.
Mike McCoy
For decades, the medical electronics community has been challenging the limits of currently available technology. Unfortunately, with relatively little volume leverage to drive technology, medical electronics has had to fund and develop pioneering technology in many arenas without the support of major manufacturers.
In other cases, the industry has had to adopt and modify technologies proven in other markets. It appears that commercial electronics, pushed largely by the wireless communications sector, has become a dominant force guiding the development of new integrated device technology. Technology emanating from wireless communications is not only applicable to many medical products but can be incorporated at a minimum of expense.
Pacemaker companies used to be world leaders in electronics miniaturization. They now can take advantage of improved miniaturization technologies driven by the manufacture of over a billion cellular telephones. New packaging technologies such as ball-grid array (BGA), chip-scale packaging (CSP), and—the current ultimate in miniaturization—the bumped flip chip, have dramatically reduced system size and improved system performance. These technologies have reduced the space necessary for integrated devices to very near the volume of the silicon die itself.
Interconnection
The remaining problem, however, has been interconnection of these miniature silicon modules. The greatest leap forward in packaging technology addresses this interconnection problem and is just now maturing. Stacking chips, typically in die form, within a BGA package has recently become extremely popular. Its popularity is partly due to its ability to unscramble the rat's nest of interconnections that inevitably occurs when connecting multiple memory devices to a separate processor.
This interconnect problem is particularly difficult when the components are all in miniature packages. Multichip packaging (MCP) is a manufacturing technique where several die are stacked and electrically bonded together into a single device. An MCP that includes logic components is being referred to as a system-in-a-package (SIP). These are becoming quite common, especially when size and weight are critical considerations.
Cellular phones and electronic medical implants are both good examples of how market pressure is forcing more features and increased performance to be squeezed into smaller packages. These smaller packages must also run for longer periods on battery power. Integration has enabled designers to address these seemingly conflicting requirements.
Integration
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| Figure 1. Cross section of a system-in-a-package multichip package. (click to enlarge) |
Previous approaches to the integration problem are often inferior to what can now be achieved by SIP. Application-specific integrated circuit (ASIC) and system-on-chip (SoC) are mature monolithic IC design approaches to achieving higher levels of integration. However, integrating various capabilities onto a single die poses many design challenges that typically result in long, costly, and risky development and production cycles.
Additionally, SoC integration often does not allow logic and memory to use the manufacturing processes best suited to those types of devices, resulting in compromises in performance of either the logic or the memory. It may also be the case that the size of the die or other factors that directly affect chip costs are not optimally balanced in the quest to integrate interrelated yet disparate system functions onto a single die.
Another point to consider is that with the SIP approach, the development of the system is not limited to the technical expertise of a particular IC manufacturer. With the SIP approach, interrelated independent components, even from different manufacturers, can be integrated more easily into an SIP than can be integrated as an SoC.
With MCP integration, a module takes the form of a single IC package that houses from two to six die. Advancements in MCP manufacturing that include die thinning, bonding, and internal connecting techniques have made this single package possible (see Figure 1). Japanese manufacturers have led the development of SIP products, especially combination memories, but manufacturers in South Korea, Taiwan, and other Asian countries are rapidly closing the gap.
Some analysts, visionaries, and industry experts expect that SIP implementations will surpass SoC implementations in the near future because of the following advantages:
- Effective use of printed circuit board area.
- Faster time-to-market for SIP modules versus SoC products.
- Reduced development cost and risk of an SIP versus an SoC.
- Improved electrical characteristics because the component interconnect wiring is shorter than would be the case for components connected on a circuit board.
- Lower overall device cost because die sizes can be optimized using appropriate manufacturing processes and because the number of explicit packages that need to be sourced and handled during device manufacturing is reduced.
- Slower IC device-size declines as technical and cost barriers arise and silicon manufacturing approaches 0.1 µm. When coupled with restrictions of package-mounting technology, this limits size reductions that can be achieved by die shrinkage alone.
Other Improvements
Perhaps the most interesting of the recent technological advances is a new variant of DRAM, commonly referred to as Pseudo SRAM (PSRAM). Really just a DRAM in SRAM clothing, these devices make low-cost DRAM technology available to a wide variety of applications that wouldn't consider a DRAM before.
These chips are among the most sophisticated memory chips in the world because they carry all of the circuitry needed to reduce their operation to SRAM-like simplicity. Designers no longer need to worry about refresh, column access strobe (CAS) and row access strobe (RAS), and all the integration requirements associated with the use of DRAMs. Rather, they simply put an address in and get data out. Once data are stored, they stay there without further intervention as long as power is maintained to the PSRAM.
| Feature | SRAM | DRAM | PSRAM |
| Ease of Use—Controls | Simple to use. Only required control signal is Write Enable. | Requires complex control signals to operate: RAS, CAS, WE, CLK, and sometimes others. | Same as SRAM. |
| Supply Tolerance | Often available in relatively wide voltage ranges. | Usually 5% or less. | Same as SRAM. |
| Refresh | None required. | Complex requirements—must cycle through periodically and interrupt other activity. | None required. |
| Speed | Similar to or can also be much faster than DRAM. | Generally slow. | Same as SRAM. |
| Density | Lags DRAM by several generations. | Leads all RAM for this criteria. | Lags DRAM about one generation and leads SRAM by at least two generations. |
| Coast | Much more expensive than DRAM on a per-bit basis. | Lowest cost. | Much cheaper than SRAM, but more expensive than DRAM. |
| Table I. Feature comparison of SRAM, DRAM, and the new PSRAM. | |||
In addition to simplifying the operation of the DRAM, other improvements can be expected from these PSRAMs as well (see Table I). Probably the most impressive is the dramatic reduction in standby power. No refresh signals need to be provided during standby, and the actual current necessary to maintain data in the cell arrays has been dramatically reduced.
Products introduced in 2002 or early 2003 are available in densities from 4 to 64 Mb. Access times are as low as 55 nanoseconds and will be even faster in the future. Standby current is an incredibly low 50 µA even at 85°C.
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| Figure 2. SRAM. |
The PSRAM achieves its characteristics through the integration of many design innovations. It achieves its low power and relatively high speed by partitioning the array into a large number of small memories and activating only a single partition for each access. This extensive partitioning is easily seen in the die photograph of Figure 2.
An internal refresh generator that is fully transparent to the operation of the PSRAM accomplishes memory cell array refresh. Basically, the refresh is carefully managed to occur between externally initiated operations without a hint of interference. Although there are a number of approaches to solving this problem, one popular approach is to refresh after data are read or written and simultaneously with the data being transferred effectively to or from the external input/output interface.
Conclusion
The medical electronics industry will change radically over the next few years as these packaging technologies and other technology improvements are absorbed. Instrumentation will become smaller, lighter, and far more powerful. Pacemakers and other such implanted devices will add significant features while reducing battery size and module weight. As always, those that adapt and change will enjoy the fruits of their foresight.
Mike McCoy is vice president of marketing, medical products, for NanoAmp Solutions (San Jose, CA). For more information, visit http://www.nanoamp.com.
Copyright ©2003 Medical Electronics Manufacturing